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https://github.com/ultravideo/uvg266.git
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New NAL unit IDs and header changes
This commit is contained in:
Marko Viitanen
parent
36eab9c170
commit
1546acfdb9
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@ -59,39 +59,55 @@ static void encoder_state_write_bitstream_PTL(bitstream_t *stream,
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{
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// PTL
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// Profile Tier
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WRITE_U(stream, 0, 2, "general_profile_space");
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// Main Profile == 1, Main 10 profile == 2, NEXT == 6
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WRITE_U(stream, 6, 7, "general_profile_idc");
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WRITE_U(stream, state->encoder_control->cfg.high_tier, 1, "general_tier_flag");
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// Main Profile == 1, Main 10 profile == 2
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WRITE_U(stream, 6, 5, "general_profile_idc");
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/* Compatibility flags should be set at general_profile_idc
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* (so with general_profile_idc = 1, compatibility_flag[1] should be 1)
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* According to specification, when compatibility_flag[1] is set,
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* compatibility_flag[2] should be set too.
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*/
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WRITE_U(stream, 3<<29, 32, "general_profile_compatibility_flag[]");
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WRITE_U(stream, 1, 1, "general_progressive_source_flag");
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WRITE_U(stream, state->encoder_control->in.source_scan_type!= 0, 1, "general_interlaced_source_flag");
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// Constraint flags
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WRITE_U(stream, 0, 1, "general_non_packed_constraint_flag");
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WRITE_U(stream, 0, 1, "general_frame_only_constraint_flag");
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WRITE_U(stream, 0, 16, "XXX_reserved_zero_43bits[0..15]");
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WRITE_U(stream, 0, 16, "XXX_reserved_zero_43bits[16..31]");
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WRITE_U(stream, 0, 11, "XXX_reserved_zero_43bits[32..42]");
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WRITE_U(stream, 0, 1, "intra_only_constraint_flag");
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WRITE_U(stream, 0, 4, "max_bitdepth_constraint_idc");
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WRITE_U(stream, 0, 2, "max_chroma_format_constraint_idc");
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WRITE_U(stream, 0, 1, "no_qtbtt_dual_tree_intra_constraint_flag");
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WRITE_U(stream, 0, 1, "reserved_zero_bit");
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WRITE_U(stream, 0, 1, "no_sao_constraint_flag");
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WRITE_U(stream, 0, 1, "no_alf_constraint_flag");
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WRITE_U(stream, 0, 1, "no_pcm_constraint_flag");
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WRITE_U(stream, 0, 1, "no_ref_wraparound_constraint_flag");
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WRITE_U(stream, 0, 1, "no_temporal_mvp_constraint_flag");
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WRITE_U(stream, 0, 1, "no_sbtmvp_constraint_flag");
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WRITE_U(stream, 0, 1, "no_amvr_constraint_flag");
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WRITE_U(stream, 0, 1, "no_bdof_constraint_flag");
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WRITE_U(stream, 0, 1, "no_cclm_constraint_flag");
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WRITE_U(stream, 0, 1, "no_mts_constraint_flag");
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WRITE_U(stream, 0, 1, "no_affine_motion_constraint_flag");
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WRITE_U(stream, 0, 1, "no_gbi_constraint_flag");
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WRITE_U(stream, 0, 1, "no_mh_intra_constraint_flag");
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WRITE_U(stream, 0, 1, "no_triangle_constraint_flag");
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WRITE_U(stream, 0, 1, "no_ladf_constraint_flag");
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WRITE_U(stream, 0, 1, "no_curr_pic_ref_constraint_flag");
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WRITE_U(stream, 0, 1, "no_qp_delta_constraint_flag");
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WRITE_U(stream, 0, 1, "no_dep_quant_constraint_flag");
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WRITE_U(stream, 0, 1, "no_sign_data_hiding_constraint_flag");
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// end Profile Tier
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uint8_t level = state->encoder_control->cfg.level;
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WRITE_U(stream, level * 3, 8, "general_level_idc");
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WRITE_U(stream, 0, 1, "sub_layer_profile_present_flag");
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WRITE_U(stream, 0, 1, "sub_layer_level_present_flag");
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for (int i = 1; i < 8; i++) {
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WRITE_U(stream, 0, 2, "reserved_zero_2bits");
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}
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WRITE_U(stream, 0, 1, "ptl_alignment_zero_bit");
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// end PTL
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}
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@ -304,15 +320,11 @@ static void encoder_state_write_bitstream_VUI(bitstream_t *stream,
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static void encoder_state_write_bitstream_SPS_extension(bitstream_t *stream,
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encoder_state_t * const state)
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{
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//const kvz_config *cfg = &state->encoder_control->cfg;
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//if (cfg->implicit_rdpcm && cfg->lossless) {
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WRITE_U(stream, 1, 1, "sps_extension_present_flag");
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WRITE_U(stream, 1, 1, "sps_range_extension_flag");
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WRITE_U(stream, 0, 1, "sps_multilayer_extension_flag");
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WRITE_U(stream, 0, 1, "sps_3d_extension_flag");
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WRITE_U(stream, 1, 1, "sps_next_extension_flag");
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WRITE_U(stream, 0, 4, "sps_extension_4bits");
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WRITE_U(stream, 0, 6, "sps_extension_6bits");
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// Range Extension
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WRITE_U(stream, 0, 1, "transform_skip_rotation_enabled_flag");
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@ -324,35 +336,8 @@ static void encoder_state_write_bitstream_SPS_extension(bitstream_t *stream,
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WRITE_U(stream, 0, 1, "high_precision_offsets_enabled_flag");
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WRITE_U(stream, 0, 1, "persistent_rice_adaptation_enabled_flag");
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WRITE_U(stream, 0, 1, "cabac_bypass_alignment_enabled_flag");
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// Next extension
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//WRITE_U(stream, 1, 1, "qtbt_flag");
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WRITE_U(stream, 0, 1, "large_ctu_flag"); // ToDo: add VVC large block support
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WRITE_U(stream, 0, 1, "subpu_tmvp_flag");
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WRITE_U(stream, 0, 1, "imv_enable_flag");
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//WRITE_U(stream, 0, 1, "high_precision_motion_vectors");
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WRITE_U(stream, 0, 1, "disable_motion_compression_flag");
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WRITE_U(stream, 0, 1, "lm_chroma_enabled_flag");
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WRITE_U(stream, 0, 1, "mts_enabled_flag");
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// IF MTS
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//WRITE_U(stream, 0, 1, "mts_intra_enabled_flag");
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//WRITE_U(stream, 0, 1, "mts_inter_enabled_flag");
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// endif
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WRITE_U(stream, 0, 1, "affine_flag");
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WRITE_U(stream, 0, 1, "gbi_flag");
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WRITE_U(stream, 0, 5, "reserved_flag_5bits");
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WRITE_U(stream, 0, 1, "mtt_enabled_flag");
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WRITE_U(stream, 0, 1, "mhintra_flag");
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WRITE_U(stream, 0, 1, "triangle_flag");
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//WRITE_U(stream, 0, 1, "next_dqp_enabled_flag");
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//} else {
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// WRITE_U(stream, 0, 1, "sps_extension_present_flag");
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// }
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WRITE_U(stream, 0, 1, "sps_reshaper_enable_flag");
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}
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static void encoder_state_write_bitstream_seq_parameter_set(bitstream_t* stream,
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@ -363,46 +348,16 @@ static void encoder_state_write_bitstream_seq_parameter_set(bitstream_t* stream,
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#ifdef KVZ_DEBUG
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printf("=========== Sequence Parameter Set ID: 0 ===========\n");
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#endif
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/*
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WRITE_UE(stream, 0, "sps_seq_parameter_set_id");
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WRITE_U(stream, 0, 1, "intra_only_constraint_flag");
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WRITE_U(stream, 0, 4, "max_bitdepth_constraint_idc");
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WRITE_U(stream, 0, 2, "max_chroma_format_constraint_idc");
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WRITE_U(stream, 0, 1, "frame_only_constraint_flag");
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WRITE_U(stream, 0, 1, "no_qtbtt_dual_tree_intra_constraint_flag");
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WRITE_U(stream, 0, 1, "no_sao_constraint_flag");
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WRITE_U(stream, 0, 1, "no_alf_constraint_flag");
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WRITE_U(stream, 0, 1, "no_pcm_constraint_flag");
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WRITE_U(stream, 0, 1, "no_ref_wraparound_constraint_flag");
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WRITE_U(stream, 0, 1, "no_temporal_mvp_constraint_flag");
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WRITE_U(stream, 0, 1, "no_sbtmvp_constraint_flag");
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WRITE_U(stream, 0, 1, "no_amvr_constraint_flag");
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WRITE_U(stream, 0, 1, "no_bdof_constraint_flag");
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WRITE_U(stream, 0, 1, "no_cclm_constraint_flag");
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WRITE_U(stream, 0, 1, "no_mts_constraint_flag");
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WRITE_U(stream, 0, 1, "no_affine_motion_constraint_flag");
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WRITE_U(stream, 0, 1, "no_gbi_constraint_flag");
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WRITE_U(stream, 0, 1, "no_mh_intra_constraint_flag");
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WRITE_U(stream, 0, 1, "no_triangle_constraint_flag");
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WRITE_U(stream, 0, 1, "no_ladf_constraint_flag");
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WRITE_U(stream, 0, 1, "no_curr_pic_ref_constraint_flag");
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WRITE_U(stream, 0, 1, "no_qp_delta_constraint_flag");
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WRITE_U(stream, 0, 1, "no_dep_quant_constraint_flag");
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WRITE_U(stream, 0, 1, "no_sign_data_hiding_constraint_flag");
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*/
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WRITE_U(stream, 1, 3, "sps_max_sub_layers_minus1");
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WRITE_U(stream, 0, 1, "sps_temporal_id_nesting_flag");
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WRITE_U(stream, 0, 5, "sps_reserved_zero_5bits");
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encoder_state_write_bitstream_PTL(stream, state);
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WRITE_UE(stream, 0, "sps_seq_parameter_set_id");
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WRITE_UE(stream, encoder->chroma_format, "chroma_format_idc");
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@ -519,7 +474,7 @@ static void encoder_state_write_bitstream_seq_parameter_set(bitstream_t* stream,
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WRITE_U(stream, 0, 1, "sps_amvr_enabled_flag");
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WRITE_U(stream, 0, 1, "sps_bdof_enabled_flag");
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WRITE_U(stream, 0, 1, "sps_affine_amvr_enabled_flag");
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WRITE_U(stream, 0, 1, "dmvr_enable_flag");
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WRITE_U(stream, 0, 1, "sps_dmvr_enable_flag");
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WRITE_U(stream, 0, 1, "lm_chroma_enabled_flag");
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@ -974,8 +929,8 @@ void kvz_encoder_state_write_bitstream_slice_header(
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WRITE_U(stream, first_slice_segment_in_pic, 1, "first_slice_segment_in_pic_flag");
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if (state->frame->pictype >= KVZ_NAL_BLA_W_LP
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&& state->frame->pictype <= KVZ_NAL_RSV_IRAP_VCL23) {
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if (state->frame->pictype >= KVZ_NAL_IDR_W_RADL
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&& state->frame->pictype <= KVZ_NAL_CRA_NUT) {
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WRITE_U(stream, 0, 1, "no_output_of_prior_pics_flag");
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}
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@ -410,58 +410,46 @@ enum kvz_nal_unit_type {
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// Trailing pictures
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KVZ_NAL_TRAIL_N = 0,
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KVZ_NAL_TRAIL_R = 1,
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KVZ_NAL_TRAIL_R = 0,
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KVZ_NAL_TSA_N = 2,
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KVZ_NAL_TSA_R = 3,
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KVZ_NAL_STSA_N = 4,
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KVZ_NAL_STSA_R = 5,
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KVZ_NAL_STSA_N = 1,
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KVZ_NAL_STSA_R = 1,
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// Leading pictures
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KVZ_NAL_RADL_N = 6,
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KVZ_NAL_RADL_R = 7,
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KVZ_NAL_RADL_N = 2,
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KVZ_NAL_RADL_R = 2,
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KVZ_NAL_RASL_N = 8,
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KVZ_NAL_RASL_R = 9,
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KVZ_NAL_RASL_N = 3,
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KVZ_NAL_RASL_R = 3,
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// Reserved non-IRAP RSV_VCL_N/R 10-15
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// Intra random access point pictures
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KVZ_NAL_BLA_W_LP = 16,
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KVZ_NAL_BLA_W_RADL = 17,
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KVZ_NAL_BLA_N_LP = 18,
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KVZ_NAL_IDR_W_RADL = 8,
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KVZ_NAL_IDR_N_LP = 9,
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KVZ_NAL_IDR_W_RADL = 19,
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KVZ_NAL_IDR_N_LP = 20,
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KVZ_NAL_CRA_NUT = 21,
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KVZ_NAL_CRA_NUT = 10,
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// Reserved IRAP
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KVZ_NAL_RSV_IRAP_VCL22 = 22,
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KVZ_NAL_RSV_IRAP_VCL23 = 23,
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KVZ_NAL_RSV_IRAP_VCL11 = 11,
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KVZ_NAL_RSV_IRAP_VCL12 = 12,
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// Reserved non-IRAP RSV_VCL 24-32
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// non-VCL
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KVZ_NAL_VPS_NUT = 32,
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KVZ_NAL_SPS_NUT = 33,
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KVZ_NAL_PPS_NUT = 34,
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KVZ_NAL_VPS_NUT = 16,
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KVZ_NAL_SPS_NUT = 17,
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KVZ_NAL_PPS_NUT = 18,
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KVZ_NAL_AUD_NUT = 35,
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KVZ_NAL_EOS_NUT = 36,
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KVZ_NAL_EOB_NUT = 37,
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KVZ_NAL_FD_NUT = 38,
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KVZ_NAL_AUD_NUT = 20,
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KVZ_NAL_EOS_NUT = 21,
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KVZ_NAL_EOB_NUT = 22,
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KVZ_NAL_PREFIX_SEI_NUT = 23,
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KVZ_NAL_SUFFIX_SEI_NUT = 24,
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KVZ_NAL_FD_NUT = 25,
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KVZ_NAL_PREFIX_SEI_NUT = 39,
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KVZ_NAL_SUFFIX_SEI_NUT = 40,
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// Reserved RSV_NVCL 41-47
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// Unspecified UNSPEC 48-63
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};
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enum kvz_slice_type {
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