mirror of
https://github.com/ultravideo/uvg266.git
synced 2024-11-27 19:24:06 +00:00
Refactor cpuid capability detection.
- Moved cpuid data to a struct to make it easier to group data from one cpuid call together. - Renamed the bit masks to make it harder to mask the wrong register or cpuid. - Remove the .byte trick. We don't really need to support such ancient compilers?
This commit is contained in:
Ari Koivula
parent
907451590e
commit
9acf7795a2
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@ -172,31 +172,44 @@ static void* strategyselector_choose_for(const strategy_list_t * const strategie
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#if COMPILE_INTEL
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#if defined(__GNUC__)
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typedef struct {
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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} cpuid_t;
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// CPUID adapters for different compilers.
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# if defined(__GNUC__)
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#include <cpuid.h>
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static INLINE int get_cpuid(unsigned int level, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
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return __get_cpuid(level, eax, ebx, ecx, edx);
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static INLINE int get_cpuid(unsigned int level, cpuid_t *cpu_info) {
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return __get_cpuid(level, &cpu_info->eax, &cpu_info->ebx, &cpu_info->ecx, &cpu_info->edx);
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}
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#else
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# elif defined(_MSC_VER)
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#include <intrin.h>
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//Adapter from __cpuid (VS) to __get_cpuid (GNU C).
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static INLINE int get_cpuid(unsigned int level, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx) {
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int CPUInfo[4] = {*eax, *ebx, *ecx, *edx};
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__cpuid(CPUInfo, 0);
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// check if the CPU supports the cpuid instruction.
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if (CPUInfo[0] != 0) {
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__cpuid(CPUInfo, level);
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*eax = CPUInfo[0];
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*ebx = CPUInfo[1];
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*ecx = CPUInfo[2];
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*edx = CPUInfo[3];
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return 1;
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}
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static INLINE int get_cpuid(unsigned int level, cpuid_t *cpu_info) {
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int vendor_info[4] = { 0, 0, 0, 0 };
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__cpuid(vendor_info, 0);
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// Check highest supported function.
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if (level > vendor_info[0]) return 0;
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int ms_cpu_info[4] = { cpu_info->eax, cpu_info->ebx, cpu_info->ecx, cpu_info->edx };
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__cpuid(ms_cpu_info, level);
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cpu_info->eax = ms_cpu_info[0];
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cpu_info->ebx = ms_cpu_info[1];
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cpu_info->ecx = ms_cpu_info[2];
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cpu_info->edx = ms_cpu_info[3];
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return 1;
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}
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# else
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static INLINE int get_cpuid(unsigned int level, cpuid_t *cpu_info)
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{
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return 0;
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}
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#endif //defined(__GNUC__)
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#endif
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# endif
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#endif // COMPILE_INTEL
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#if COMPILE_POWERPC
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#include <unistd.h>
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@ -244,54 +257,68 @@ static void set_hardware_flags(int32_t cpuid) {
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#if COMPILE_INTEL
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if (cpuid) {
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unsigned int eax = 0, ebx = 0, ecx = 0, edx =0;
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cpuid_t cpuid1 = { 0, 0, 0, 0 };
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/* CPU feature bits */
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enum { BIT_SSE3 = 0, BIT_SSSE3 = 9, BIT_SSE41 = 19, BIT_SSE42 = 20,
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BIT_MMX = 24, BIT_SSE = 25, BIT_SSE2 = 26,
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BIT_OSXSAVE = 27, BIT_AVX = 28};
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enum { XCR0_XMM = 1, XCR0_YMM = 2 };
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enum {
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CPUID1_EDX_MMX = 1 << 23,
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CPUID1_EDX_SSE = 1 << 25,
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CPUID1_EDX_SSE2 = 1 << 26,
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};
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enum {
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CPUID1_ECX_SSE3 = 1 << 0,
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CPUID1_ECX_SSSE3 = 1 << 9,
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CPUID1_ECX_SSE41 = 1 << 19,
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CPUID1_ECX_SSE42 = 1 << 20,
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CPUID1_ECX_XSAVE = 1 << 26,
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CPUID1_ECX_OSXSAVE = 1 << 27,
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CPUID1_ECX_AVX = 1 << 28,
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};
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enum {
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CPUID7_EBX_AVX2 = 1 << 5,
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};
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enum {
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XGETBV_XCR0_XMM = 1 << 1,
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XGETBV_XCR0_YMM = 1 << 2,
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};
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// Dig CPU features with cpuid
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get_cpuid(1, &eax, &ebx, &ecx, &edx);
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get_cpuid(1, &cpuid1);
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// EDX
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if (edx & (1<<BIT_MMX)) g_hardware_flags.intel_flags.mmx = 1;
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if (edx & (1<<BIT_SSE)) g_hardware_flags.intel_flags.sse = 1;
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if (edx & (1<<BIT_SSE2)) g_hardware_flags.intel_flags.sse2 = 1;
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if (cpuid1.edx & CPUID1_EDX_MMX) g_hardware_flags.intel_flags.mmx = 1;
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if (cpuid1.edx & CPUID1_EDX_SSE) g_hardware_flags.intel_flags.sse = 1;
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if (cpuid1.edx & CPUID1_EDX_SSE2) g_hardware_flags.intel_flags.sse2 = 1;
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// ECX
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if (ecx & (1<<BIT_SSE3)) g_hardware_flags.intel_flags.sse3 = 1;;
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if (ecx & (1<<BIT_SSSE3)) g_hardware_flags.intel_flags.ssse3 = 1;
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if (ecx & (1<<BIT_SSE41)) g_hardware_flags.intel_flags.sse41 = 1;
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if (ecx & (1<<BIT_SSE42)) g_hardware_flags.intel_flags.sse42 = 1;
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if (cpuid1.ecx & CPUID1_ECX_SSE3) g_hardware_flags.intel_flags.sse3 = 1;;
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if (cpuid1.ecx & CPUID1_ECX_SSSE3) g_hardware_flags.intel_flags.ssse3 = 1;
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if (cpuid1.ecx & CPUID1_ECX_SSE41) g_hardware_flags.intel_flags.sse41 = 1;
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if (cpuid1.ecx & CPUID1_ECX_SSE42) g_hardware_flags.intel_flags.sse42 = 1;
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// Check hardware and OS support for AVX.
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if (ecx & (1 << BIT_OSXSAVE)) {
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// Check hardware and OS support for xsave and xgetbv.
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if (cpuid1.ecx & (CPUID1_ECX_XSAVE | CPUID1_ECX_OSXSAVE)) {
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uint64_t xcr0 = 0;
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// Use _XCR_XFEATURE_ENABLED_MASK to check if _xgetbv intrinsic is
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// supported by the compiler.
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#ifdef _XCR_XFEATURE_ENABLED_MASK
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xcr0 = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
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#elif defined(__GNUC__)
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uint32_t geax = 0;
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// Apparently there are some older assemblers that don't support xgetbv,
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// so we use the byte sequence for xgetbv just in case.
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//__asm__("xgetbv" : "=a" (geax), "=d" (gedx) : "c" (0));
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__asm__(".byte 0x0f, 0x01, 0xd0" : "=a" (geax) : "c" (0) : "edx");
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// edx is spillover, but we don't care about those bits.
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xcr0 = geax;
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unsigned eax = 0, edx = 0;
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asm("xgetbv" : "=a"(eax), "=d"(edx) : "c" (0));
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xcr0 = (uint64_t)edx << 32 | eax;
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#endif
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bool avx_support = ecx & (1 << BIT_AVX) || false;
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bool xmm_support = xcr0 & (1 << XCR0_XMM);
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bool ymm_support = xcr0 & (1 << XCR0_YMM);
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bool avx_support = cpuid1.ecx & CPUID1_ECX_AVX || false;
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bool xmm_support = xcr0 & XGETBV_XCR0_XMM || false;
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bool ymm_support = xcr0 & XGETBV_XCR0_YMM || false;
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if (avx_support && xmm_support && ymm_support) {
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g_hardware_flags.intel_flags.avx = 1;
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}
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}
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if (g_hardware_flags.intel_flags.avx) {
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get_cpuid(7, &eax, &ebx, &ecx, &edx);
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if (ebx & (1 << 5)) g_hardware_flags.intel_flags.avx2 = 1;
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if (g_hardware_flags.intel_flags.avx) {
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cpuid_t cpuid7 = { 0, 0, 0, 0 };
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get_cpuid(7, &cpuid7);
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if (cpuid7.ebx & CPUID7_EBX_AVX2) g_hardware_flags.intel_flags.avx2 = 1;
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}
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}
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}
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