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[mtt] Fix couple of issues with 64x32 CUs and non square tr skip rdoq
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@ -237,7 +237,7 @@ void uvg_encode_ts_residual(encoder_state_t* const state,
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const uint32_t log2_block_width = uvg_g_convert_to_log2[width];
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const uint32_t log2_block_height = uvg_g_convert_to_log2[height];
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// TODO: log2_cg_size is wrong if width != height
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const uint32_t log2_cg_size = uvg_g_log2_sbb_size[log2_block_width][log2_block_width][0] + uvg_g_log2_sbb_size[log2_block_width][log2_block_width][1];
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const uint32_t log2_cg_size = uvg_g_log2_sbb_size[log2_block_width][log2_block_width][0] + uvg_g_log2_sbb_size[log2_block_width][log2_block_height][1];
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const uint32_t* const scan = uvg_get_scan_order_table(SCAN_GROUP_4X4, scan_mode, log2_block_width, log2_block_height);
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const uint32_t* const scan_cg = uvg_get_scan_order_table(SCAN_GROUP_UNGROUPED, scan_mode, log2_block_width, log2_block_height);
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@ -265,7 +265,7 @@ void uvg_encode_ts_residual(encoder_state_t* const state,
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bool no_sig_group_before_last = true;
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for (i = 0; i <= scan_cg_last; i++) {
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if (!(width == 4 || (i ==scan_cg_last && no_sig_group_before_last))) {
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if (!((width == 4 && height == 4) || (i ==scan_cg_last && no_sig_group_before_last))) {
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uint32_t cg_blkpos = scan_cg[i];
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uint32_t cg_pos_y = cg_blkpos / cg_width;
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uint32_t cg_pos_x = cg_blkpos - (cg_pos_y * cg_width);
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@ -129,7 +129,7 @@ typedef int16_t coeff_t;
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typedef int16_t mv_t;
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//#define VERBOSE 1
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//#define UVG_DEBUG_PRINT_CABAC 1
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#define UVG_DEBUG_PRINT_CABAC 1
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//#define UVG_DEBUG 1
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//#define UVG_DEBUG_PRINT_YUVIEW_CSV 1
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@ -1649,7 +1649,7 @@ void uvg_intra_predict(
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}
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else {
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uvg_pixels_blit(&state->tile->frame->cclm_luma_rec[x / 2 + (y * stride) / 4], dst, width, height, stride / 2, width);
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if (!PU_IS_TU(&data->pred_cu) || data->cclm_parameters[color == COLOR_U ? 0 : 1].b <= 0) {
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if (width != 1 << data->pred_cu.log2_chroma_width || height != 1 << data->pred_cu.log2_chroma_height || data->cclm_parameters[color == COLOR_U ? 0 : 1].b <= 0) {
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predict_cclm(
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state, color, width, height, x, y, stride, intra_mode, lcu, refs, dst,
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(cclm_parameters_t*)&data->cclm_parameters[color == COLOR_U ? 0 : 1],
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@ -1196,8 +1196,11 @@ int uvg_ts_rdoq(encoder_state_t* const state, coeff_t* src_coeff, coeff_t* dest_
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switch (cg_num) {
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case 1: FILL_ARRAY(sig_coeffgroup_flag, 0, 1); FILL_ARRAY(cost_coeffgroup_sig, 0, 1); break;
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case 2: FILL_ARRAY(sig_coeffgroup_flag, 0, 2); FILL_ARRAY(cost_coeffgroup_sig, 0, 2); break;
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case 4: FILL_ARRAY(sig_coeffgroup_flag, 0, 4); FILL_ARRAY(cost_coeffgroup_sig, 0, 4); break;
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case 8: FILL_ARRAY(sig_coeffgroup_flag, 0, 8); FILL_ARRAY(cost_coeffgroup_sig, 0, 8); break;
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case 16: FILL_ARRAY(sig_coeffgroup_flag, 0, 16); FILL_ARRAY(cost_coeffgroup_sig, 0, 16); break;
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case 32: FILL_ARRAY(sig_coeffgroup_flag, 0, 32); FILL_ARRAY(cost_coeffgroup_sig, 0, 32); break;
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case 64: FILL_ARRAY(sig_coeffgroup_flag, 0, 64); FILL_ARRAY(cost_coeffgroup_sig, 0, 64); break;
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default: assert(0 && "There should be 1, 4, 16 or 64 coefficient groups");
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}
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@ -341,6 +341,7 @@ static double search_intra_trdepth(
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if (state->encoder_control->cfg.trskip_enable
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&& width <= (1 << state->encoder_control->cfg.trskip_max_size)
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&& height <= (1 << state->encoder_control->cfg.trskip_max_size)
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&& PU_IS_TU(pred_cu)
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&& pred_cu->intra.isp_mode == ISP_MODE_NO_ISP) {
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num_transforms = MAX(num_transforms, 2);
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}
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@ -378,6 +379,7 @@ static double search_intra_trdepth(
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if (trafo == MTS_SKIP && ((width > (1 << state->encoder_control->cfg.trskip_max_size)
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|| (height > (1 << state->encoder_control->cfg.trskip_max_size)))
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|| !PU_IS_TU(pred_cu)
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|| !state->encoder_control->cfg.trskip_enable)) {
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continue;
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}
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