mirror of
https://github.com/ultravideo/uvg266.git
synced 2024-11-27 11:24:05 +00:00
Reconfigure VS project.
- Moved compilation flag stuff from project file to the abstraction layer. - Disabled randomized base address as unnecessary. - Disable stack buffer security check from release.
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@ -22,6 +22,7 @@
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<AdditionalDependencies>%(AdditionalDependencies)</AdditionalDependencies>
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<GenerateDebugInformation>true</GenerateDebugInformation>
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<SubSystem>Console</SubSystem>
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<RandomizedBaseAddress>false</RandomizedBaseAddress>
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</Link>
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</ItemDefinitionGroup>
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<ItemGroup />
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@ -12,7 +12,7 @@
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<FavorSizeOrSpeed>Speed</FavorSizeOrSpeed>
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<IntrinsicFunctions>true</IntrinsicFunctions>
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<RuntimeLibrary>MultiThreadedDLL</RuntimeLibrary>
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<PreprocessorDefinitions>__MMX__;__SSE__;__SSE2__;__SSSE3__;__SSE4_1__;__SSE4_2__;__AVX__;%(PreprocessorDefinitions)</PreprocessorDefinitions>
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<BufferSecurityCheck>false</BufferSecurityCheck>
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</ClCompile>
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</ItemDefinitionGroup>
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<ItemGroup />
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@ -26,59 +26,64 @@
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//Hardware data (abstraction of defines). Extend for other compilers
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#if defined(_M_IX86) || defined(__i586__) || defined(__i686__) || defined(_M_X64) || defined(_M_AMD64) || defined(__amd64__) || defined(__x86_64__)
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#define COMPILE_INTEL 1
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#if defined(__MMX__)
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#define COMPILE_INTEL_MMX 1
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#endif
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#if defined(__SSE__)
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#define COMPILE_INTEL_SSE 1
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#endif
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#if defined(__SSE2__)
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#define COMPILE_INTEL_SSE2 1
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#endif
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#if defined(__SSE3__)
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#define COMPILE_INTEL_SSE3 1
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#endif
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#if defined(__SSSE3__)
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#define COMPILE_INTEL_SSSE3 1
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#endif
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#if defined(__SSE4_1__)
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#define COMPILE_INTEL_SSE41 1
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#endif
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#if defined(__SSE4_2__)
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#define COMPILE_INTEL_SSE42 1
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#endif
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#if defined(__AVX__)
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#define COMPILE_INTEL_AVX 1
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#endif
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# define COMPILE_INTEL 1
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#else
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#define COMPILE_INTEL 0
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# define COMPILE_INTEL 0
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#endif
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// Visual Studio note:
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// Because these macros are only used to guard code that is guarded by CPUID
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// at runtime, use /arch parameter to disable them, but enable all intrinsics
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// supported by VisualStudio if SSE2 (highest) is enabled.
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// AVX and AVX2 are handled by /arch directly and sse intrinsics will use VEX
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// versions if they are defined.
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#define MSC_X86_SIMD(level) (_M_X64 || (_M_IX86_FP >= (level)))
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#if COMPILE_INTEL
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# if defined(__MMX__) || MSC_X86_SIMD(1)
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# define COMPILE_INTEL_MMX 1
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# endif
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# if defined(__SSE__) || MSC_X86_SIMD(1)
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# define COMPILE_INTEL_SSE 1
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# endif
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# if defined(__SSE2__) || MSC_X86_SIMD(2)
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# define COMPILE_INTEL_SSE2 1
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# endif
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# if defined(__SSE3__)
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# define COMPILE_INTEL_SSE3 1
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# endif
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# if defined(__SSSE3__) || MSC_X86_SIMD(2)
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# define COMPILE_INTEL_SSSE3 1
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# endif
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# if defined(__SSE4_1__) || MSC_X86_SIMD(2)
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# define COMPILE_INTEL_SSE41 1
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# endif
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# if defined(__SSE4_2__) || MSC_X86_SIMD(2)
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# define COMPILE_INTEL_SSE42 1
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# endif
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# if defined(__AVX__)
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# define COMPILE_INTEL_AVX 1
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# endif
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# if defined(__AVX2__)
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# define COMPILE_INTEL_AVX2 1
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# endif
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#endif
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#if defined (_M_PPC) || defined(__powerpc64__) || defined(__powerpc__)
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#define COMPILE_POWERPC 1
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#ifdef __ALTIVEC__
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#define COMPILE_POWERPC_ALTIVEC 1
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# define COMPILE_POWERPC 1
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# ifdef __ALTIVEC__
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# define COMPILE_POWERPC_ALTIVEC 1
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# else
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# define COMPILE_POWERPC_ALTIVEC 0
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# endif
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#else
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#define COMPILE_POWERPC_ALTIVEC 0
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#endif
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#else
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#define COMPILE_POWERPC 0
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# define COMPILE_POWERPC 0
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#endif
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#if defined (_M_ARM) || defined(__arm__) || defined(__thumb__)
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#define COMPILE_ARM 1
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# define COMPILE_ARM 1
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#else
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#define COMPILE_ARM 0
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# define COMPILE_ARM 0
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#endif
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