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Author SHA1 Message Date
Reima Hyvönen 99dc43074f _mm256_cvtsi256_si32 breaks system, too much bits. back to extract 2018-08-10 09:59:33 +03:00
Reima Hyvönen 4f1f80b2cb Transformed convert from 256 to cast 256 -> 128 and then convert from 128 2018-08-09 15:35:54 +03:00
Reima Hyvönen 4957555eb3 Removed leftover from 939 2018-08-09 15:25:03 +03:00
Reima Hyvönen 28b165c971 Clearified some sections, added _MM_SHUFFLE macro 2018-08-09 15:23:01 +03:00
Reima Hyvönen dd04df8667 testing if error in both avx2 functions 2018-08-03 11:49:00 +03:00
Reima Hyvönen ed50d71fde Switched some variables to different location, altered inter_recon_bipred_avx2 function 2018-08-02 16:08:59 +03:00
Reima Hyvönen 9ba85ab7b0 Testing if test break pipeline 2018-08-02 14:55:20 +03:00
Reima Hyvönen f5739a0028 Renaming and removing useless prints 2018-08-02 14:47:17 +03:00
Reima Hyvönen bc09f59bb6 Edited some definitions 2018-08-02 11:54:53 +03:00
Marko Viitanen 6a479f8249 Added debugging example to README 2018-07-27 14:44:15 +03:00
Marko Viitanen ffbc178cf9 An attempt to fix checksums 2018-07-27 14:38:05 +03:00
Marko Viitanen 84b6a61193 Hack to fix split flag model for PCM use -> valid VVC bitstream 2018-07-27 14:29:31 +03:00
Marko Viitanen 90174f1143 Add more values to cabac debugging 2018-07-27 13:59:54 +03:00
Marko Viitanen c6572d644f Updated split_flag initialization to support Large CTUs in VVC 2018-07-27 12:32:45 +03:00
Marko Viitanen 7abadaafe4 Disable CTU splitting and configure max CTU sizes to 64x64 2018-07-27 11:04:21 +03:00
Marko Viitanen 6921e31502 Fix debugging functions 2018-07-27 11:03:16 +03:00
Marko Viitanen 37b5ce3d33 Change configurations to ease VVC debugging, max-BT-depth = 0 2018-07-26 16:12:11 +03:00
Marko Viitanen 792da1b7e0 Force PCM coding and fix PCM sample output 2018-07-26 11:05:31 +03:00
Marko Viitanen 5d4a2a004f Remove depentent slice, wpp/tile and scaling list parameters from PPS 2018-07-26 10:43:21 +03:00
Marko Viitanen 31a6cbfe6d Disable sign bit hiding 2018-07-26 10:41:35 +03:00
Marko Viitanen 9f2b429c66 Disable some features not used in VVC 
- Part mode coding not used
 - split transform flag not used
 - last significant coeff pos swapping not used
 2018-07-26 10:33:27 +03:00
Marko Viitanen e84276f7f6 Fixed version string 2018-07-26 08:17:55 +03:00
Marko Viitanen e38109d102 Enable QTBT and set correct general_profile_idc for Next 2018-07-25 12:24:17 +03:00
Marko Viitanen 079ca9b8b2 Disable tile/wpp flags in slice header 2018-07-25 11:19:53 +03:00
Marko Viitanen b0ac7002e5 Disable VPS 2018-07-25 11:02:09 +03:00
Marko Viitanen c5bf6a3774 Bugfix: add missing parameters to WRITE_U 2018-07-25 10:18:48 +03:00
Marko Viitanen 9befe35961 Modify slice header to conform VVC 2018-07-25 10:17:42 +03:00
Marko Viitanen 95ce1e1a25 Modify parameter sets to conform VVC 2018-07-25 10:05:11 +03:00
Arttu Ylä-Outinen 9d22c1ec3e Merge branch 'coeff-cost-estimation' 2018-07-17 10:56:50 +03:00
Arttu Ylä-Outinen 83555c3d6d Enable --fast-residual-cost with fastest presets 2018-07-16 12:31:20 +03:00
Arttu Ylä-Outinen c438bb4a19 Add an option to skip CABAC for residual costs 
Adds command line option --fast-residual-cost=<limit>. When QP is below
the limit, estimates the cost of coding the residual coefficients from
the sum of absolute coefficients. Skipping CABAC is not worth it with
high QPs because there are fewer coefficients so CABAC is not as slow.
 2018-07-16 12:31:20 +03:00
Reima Hyvönen 08f4ebdcda Merge branch 'bipred_recon' of https://gitlab.tut.fi/TIE/ultravideo/kvazaar 2018-07-12 09:30:15 +03:00
Reima Hyvönen a4bf77f208 Tested some extract functions 2018-07-12 09:29:32 +03:00
Reima Hyvönen 7f18c12227 testing pipelining 2018-07-11 15:16:23 +03:00
Reima Hyvönen c05033a893 Even more useless vectors removed 2018-07-11 15:09:14 +03:00
Reima Hyvönen 884cb77238 Removed some not used vectors 2018-07-11 15:06:11 +03:00
Reima Hyvönen 792689a5ff Removed for-loops, added extract instead 2018-07-11 14:56:41 +03:00
Reima Hyvönen f9c7f6ee66 Added some break-operations for avx2 optimation 2018-07-11 14:15:38 +03:00
Reima Hyvönen cc064da143 some more optimation for bipred 2018-07-11 11:27:54 +03:00
Reima Hyvönen 9a339eef89 Merge branch 'bipred_recon' of https://gitlab.tut.fi/TIE/ultravideo/kvazaar into HEAD 
# Conflicts:
#	build/kvazaar_lib/kvazaar_lib.vcxproj
 2018-07-10 16:21:04 +03:00
Reima Hyvönen a22cf03ddb Updated to have no movement function to avx2 strategies 2018-07-10 16:07:15 +03:00
Arttu Ylä-Outinen cbb5b20449 Merge branch 'gitlab-ci-fix' 2018-07-06 08:59:55 +03:00
Arttu Ylä-Outinen 31786a9266 Fix ASan test on Gitlab CI 
Changes test_external_symbols.sh to expect a failure with ASan.
 2018-07-05 16:05:55 +03:00
Arttu Ylä-Outinen b7474eb532 Fix SAO buffer sizes 
Increases sizes of buffers used for SAO reconstruction to avoid stack
buffer overflow in AVX2 SAO reconstruction.
 2018-07-05 15:56:30 +03:00
Arttu Ylä-Outinen 120f285eb7 Fix Gitlab CI tests 
Drops the build stage in Gitlab CI tests and includes build in the test
jobs. Building in a separate stage did not work as intended. The test
jobs rebuilt Kvazaar without the CFLAGS given in the build jobs and
overwrote the results from the build jobs. The test were therefore run
without the sanitizers enabled.
 2018-07-05 14:44:15 +03:00
Arttu Ylä-Outinen b37470e80f
Merge pull request #207 from jbeich/maltivec 
Unbreak build on PowerPC if AltiVec isn't supported
 2018-07-04 11:06:41 +03:00
Arttu Ylä-Outinen ee27d9359b
Merge pull request #206 from jbeich/powerpc 
Clean up macOS includes in src/strategyselector.c
 2018-07-04 11:05:07 +03:00
Reima Hyvönen ea83ae45f0 Toimiva ratkaisu 2018-07-03 11:18:51 +03:00
Jan Beich 4f4bea7496 Check -maltivec is supported before using 
PowerPC target may lack or have non-standard FPU:

$ cc -dumpmachine
powerpcspe-undermydesk-freebsd
$ cc -c -maltivec -Isrc src/strategies/altivec/picture-altivec.c
src/strategies/altivec/picture-altivec.c:1: error: AltiVec and E500 instructions cannot coexist
 2018-07-02 23:25:23 +00:00
Jan Beich b892d820f8 Clean up macOS includes on powerpc* after 93e1c9f1c3 
strategyselector.c:426:25: machine/cpu.h: No such file or directory
 2018-07-02 21:52:45 +00:00