hashirama/xserver
Watch
0
0
Fork
You've already forked xserver
 0
mirror of https://github.com/X11Libre/xserver.git synced 2026-10-21 01:13:38 +00:00
Code Issues Projects Releases Wiki Activity

Fix remaining ruff check issues

Browse source 
Two if conditions compressed into one.
Two open() marked as ignored by SIM115 (use context manager for opening files)
because it'd require too much restructuring.
And one open() ... close()  changed to a context manager, the diff
is the reindentation of everything between open and close.

Part-of: <https://gitlab.freedesktop.org/xorg/xserver/-/merge_requests/2327>
(cherry picked from commit eb9292efdb)

Signed-off-by: Peter Hutterer <peter.hutterer@who-t.net>
This commit is contained in:
Peter Hutterer 2026-09-17 10:20:42 +10:00 • committed by Enrico Weigelt
commit 9e3b288abf
1 changed files with 38 additions and 39 deletions
Download patch file Download diff file Expand all files Collapse all files

71
hw/xwin/glx/gen_gl_wrappers.py
View file

@ -122,10 +122,10 @@ genOpts = CGeneratorOptions(
# create error/warning & diagnostic files
if errFilename:
errWarn = open(errFilename, "w")
errWarn = open(errFilename, "w") # noqa: SIM115
else:
errWarn = sys.stderr
diag = open(diagFilename, "w")
diag = open(diagFilename, "w") # noqa: SIM115
def ParseCmdRettype(cmd):
@ -477,9 +477,7 @@ class ShimOutputGenerator(OutputGenerator):
self.outFile.write(f' RESOLVE(PFN{name.upper()}PROC, "{name}");\n')
self.outFile.write(" RESOLVED_PROC(")
else:
self.outFile.write(
f' RESOLVE_RET(PFN{name.upper()}PROC, "{name}", 0);\n'
)
self.outFile.write(f' RESOLVE_RET(PFN{name.upper()}PROC, "{name}", 0);\n')
self.outFile.write(" return RESOLVED_PROC(")
Comma = ""
@ -491,41 +489,42 @@ class ShimOutputGenerator(OutputGenerator):
def genHeaders():
outFile = open(outFilename, "w")
with open(outFilename, "w") as outFile:
if preresolve:
gen = PreResolveOutputGenerator(
errFile=errWarn, warnFile=errWarn, diagFile=diag
)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
if preresolve:
gen = PreResolveOutputGenerator(
errFile=errWarn, warnFile=errWarn, diagFile=diag
)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
if wrapper:
gen = WrapperOutputGenerator(
errFile=errWarn, warnFile=errWarn, diagFile=diag
)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
if wrapper:
gen = WrapperOutputGenerator(errFile=errWarn, warnFile=errWarn, diagFile=diag)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
if shim:
gen = ShimOutputGenerator(errFile=errWarn, warnFile=errWarn, diagFile=diag)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
if shim:
gen = ShimOutputGenerator(errFile=errWarn, warnFile=errWarn, diagFile=diag)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
if thunk:
gen = ThunkOutputGenerator(errFile=errWarn, warnFile=errWarn, diagFile=diag)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
if thunk:
gen = ThunkOutputGenerator(errFile=errWarn, warnFile=errWarn, diagFile=diag)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
if thunkdefs:
gen = ThunkDefsOutputGenerator(errFile=errWarn, warnFile=errWarn, diagFile=diag)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
outFile.close()
if thunkdefs:
gen = ThunkDefsOutputGenerator(
errFile=errWarn, warnFile=errWarn, diagFile=diag
)
gen.outFile = outFile
reg.setGenerator(gen)
reg.apiGen(genOpts)
genHeaders()