mirror of
https://github.com/X11Libre/xserver.git
synced 2026-10-17 00:32:57 +00:00
Modifying X.Org Xserver DDX to allow to run X with ordinary user
permissions when no access to HW registers is required. For API changes
which mostly involve the modifications to make the RRFunc (introduced
with 6.8) more flexible please check Bugzilla #2407. NOTE: This patch
applies changes to OS specific files for other OSes which I cannot
test.
This commit is contained in:
Egbert Eich
parent
1562ec5cc3
commit
d23c46dd3e
27 changed files with 539 additions and 327 deletions
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@ -208,13 +208,6 @@
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#define PCI_MFDEV_SUPPORT 1 /* Include PCI multifunction device support */
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#define PCI_BRIDGE_SUPPORT 1 /* Include support for PCI-to-PCI bridges */
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#ifdef PC98
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#define outb(port,data) _outb(port,data)
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#define outl(port,data) _outl(port,data)
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#define inb(port) _inb(port)
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#define inl(port) _inl(port)
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#endif
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/*
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* Global data
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*/
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@ -833,90 +826,6 @@ pciGenFindFirst(void)
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return pciGenFindNext();
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}
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#if defined (__powerpc__)
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static int buserr_detected;
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static
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void buserr(int sig)
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{
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buserr_detected = 1;
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}
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#endif
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CARD32
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pciCfgMech1Read(PCITAG tag, int offset)
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{
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unsigned long rv = 0xffffffff;
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Read(tag=%08x,offset=%08x)\n", tag, offset);
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#endif
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#if defined(__powerpc__)
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signal(SIGBUS, buserr);
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buserr_detected = 0;
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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rv = inl(0xCFC);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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if (buserr_detected)
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{
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Read() BUS ERROR\n");
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#endif
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return(0xffffffff);
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}
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else
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#endif
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return(rv);
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}
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void
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pciCfgMech1Write(PCITAG tag, int offset, CARD32 val)
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{
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Write(tag=%08x,offset=%08x,val=%08x)\n",
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tag, offset,val);
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#endif
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_IGN);
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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#if defined(Lynx) && defined(__powerpc__)
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outb(0x80, 0x00); /* without this the next access fails
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* on my Powerstack system when we use
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* assembler inlines for outl */
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#endif
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outl(0xCFC, val);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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#endif
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}
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void
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pciCfgMech1SetBits(PCITAG tag, int offset, CARD32 mask, CARD32 val)
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{
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unsigned long rv = 0xffffffff;
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#if defined(__powerpc__)
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signal(SIGBUS, buserr);
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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rv = inl(0xCFC);
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rv = (rv & ~mask) | val;
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outl(0xCFC, rv);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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#endif
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}
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CARD32
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pciByteSwap(CARD32 u)
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{
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@ -140,6 +140,7 @@
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#include "compiler.h"
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#include "xf86.h"
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#include "xf86Priv.h"
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#include "xf86_OSlib.h"
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#include "Pci.h"
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#ifdef PC98
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@ -278,6 +279,8 @@ void ix86PciSelectCfgmech(void)
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#endif
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case PCIProbe1:
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if (!xf86EnableIO())
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return;
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xf86MsgVerb(X_INFO, 2,
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"PCI: Probing config type using method 1\n");
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@ -449,6 +452,8 @@ void ix86PciSelectCfgmech(void)
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break; /* } */
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case PCIProbe2: /* { */
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if (!xf86EnableIO())
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return;
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/* The scanpci-style detection method */
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@ -481,6 +486,8 @@ void ix86PciSelectCfgmech(void)
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break; /* } */
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case PCIForceConfig1:
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if (!xf86EnableIO())
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return;
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xf86MsgVerb(X_INFO, 2, "PCI: Forcing config type 1\n");
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@ -490,6 +497,8 @@ void ix86PciSelectCfgmech(void)
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return;
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case PCIForceConfig2:
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if (!xf86EnableIO())
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return;
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xf86MsgVerb(X_INFO, 2, "PCI: Forcing config type 2\n");
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@ -99,9 +99,9 @@ linuxPciInit()
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}
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static int
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linuxPciOpenFile(PCITAG tag)
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linuxPciOpenFile(PCITAG tag, Bool write)
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{
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static int lbus,ldev,lfunc,fd = -1;
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static int lbus,ldev,lfunc,fd = -1,is_write = 0;
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int bus, dev, func;
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char file[32];
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struct stat ignored;
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@ -109,7 +109,8 @@ linuxPciOpenFile(PCITAG tag)
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bus = PCI_BUS_FROM_TAG(tag);
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dev = PCI_DEV_FROM_TAG(tag);
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func = PCI_FUNC_FROM_TAG(tag);
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if (fd == -1 || bus != lbus || dev != ldev || func != lfunc) {
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if (fd == -1 || (write && (!is_write))
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|| bus != lbus || dev != ldev || func != lfunc) {
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if (fd != -1)
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close(fd);
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if (bus < 256) {
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@ -129,7 +130,19 @@ linuxPciOpenFile(PCITAG tag)
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sprintf(file, "/proc/bus/pci/%04x/%02x.%1x",
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bus, dev, func);
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}
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fd = open(file,O_RDWR);
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if (write) {
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fd = open(file,O_RDWR);
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if (fd != -1) is_write = TRUE;
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} else switch (is_write) {
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case TRUE:
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fd = open(file,O_RDWR);
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if (fd > -1)
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break;
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default:
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fd = open(file,O_RDONLY);
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is_write = FALSE;
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}
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lbus = bus;
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ldev = dev;
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lfunc = func;
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@ -143,7 +156,7 @@ linuxPciCfgRead(PCITAG tag, int off)
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int fd;
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CARD32 val = 0xffffffff;
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if (-1 != (fd = linuxPciOpenFile(tag))) {
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if (-1 != (fd = linuxPciOpenFile(tag,FALSE))) {
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lseek(fd,off,SEEK_SET);
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read(fd,&val,4);
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}
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@ -155,7 +168,7 @@ linuxPciCfgWrite(PCITAG tag, int off, CARD32 val)
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{
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int fd;
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if (-1 != (fd = linuxPciOpenFile(tag))) {
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if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) {
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lseek(fd,off,SEEK_SET);
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val = PCI_CPU(val);
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write(fd,&val,4);
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@ -168,7 +181,7 @@ linuxPciCfgSetBits(PCITAG tag, int off, CARD32 mask, CARD32 bits)
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int fd;
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CARD32 val = 0xffffffff;
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if (-1 != (fd = linuxPciOpenFile(tag))) {
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if (-1 != (fd = linuxPciOpenFile(tag,TRUE))) {
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lseek(fd,off,SEEK_SET);
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read(fd,&val,4);
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val = PCI_CPU(val);
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@ -336,7 +349,7 @@ xf86GetPciDomain(PCITAG Tag)
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if (pPCI && (result = PCI_DOM_FROM_BUS(pPCI->busnum)))
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return result;
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if ((fd = linuxPciOpenFile(pPCI ? pPCI->tag : 0)) < 0)
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if ((fd = linuxPciOpenFile(pPCI ? pPCI->tag : 0,FALSE)) < 0)
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return 0;
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if ((result = ioctl(fd, PCIIOC_CONTROLLER, 0)) < 0)
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@ -359,7 +372,7 @@ linuxMapPci(int ScreenNum, int Flags, PCITAG Tag,
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pPCI = xf86GetPciHostConfigFromTag(Tag);
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if (((fd = linuxPciOpenFile(pPCI ? pPCI->tag : 0)) < 0) ||
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if (((fd = linuxPciOpenFile(pPCI ? pPCI->tag : 0,FALSE)) < 0) ||
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(ioctl(fd, mmap_ioctl, 0) < 0))
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break;
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@ -1,4 +1,4 @@
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/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ppcPci.c,v 1.9 2002/08/27 22:07:07 tsi Exp $ */
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/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/ppcPci.c,v 1.8 2002/07/24 19:06:52 tsi Exp $ */
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/*
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* ppcPci.c - PowerPC PCI access functions
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*
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@ -78,14 +78,15 @@ ppcPciInit()
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pmaxPciInit();
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#else
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extern void motoppcPciInit(void);
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static void motoppcPciInit(void);
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motoppcPciInit();
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#endif
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}
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#if defined(PowerMAX_OS)
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/*
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* Motorola PowerPC platform support
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*
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@ -101,6 +102,11 @@ ppcPciInit()
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*/
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static ADDRESS motoppcBusAddrToHostAddr(PCITAG, PciAddrType, ADDRESS);
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static ADDRESS motoppcHostAddrToBusAddr(PCITAG, PciAddrType, ADDRESS);
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static CARD32 pciCfgMech1Read(PCITAG tag, int offset);
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static void pciCfgMech1Write(PCITAG tag, int offset, CARD32 val);
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static void pciCfgMech1SetBits(PCITAG tag, int offset,
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CARD32 mask, CARD32 val);
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static pciBusFuncs_t motoppcFuncs0 = {
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/* pciReadLong */ pciCfgMech1Read,
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@ -126,7 +132,7 @@ static pciBusInfo_t motoppcPci0 = {
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extern volatile unsigned char *ioBase;
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void
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static void
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motoppcPciInit()
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{
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pciNumBuses = 1;
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@ -134,6 +140,9 @@ motoppcPciInit()
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pciFindFirstFP = pciGenFindFirst;
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pciFindNextFP = pciGenFindNext;
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if (!xf86EnableIO())
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FatalError("motoppcPciInit: EnableIO failed\n");
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if (ioBase == MAP_FAILED) {
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ppcPciIoMap(0); /* Make inb/outb et al work for pci0 and its secondaries */
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@ -210,3 +219,89 @@ motoppcHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr)
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/*NOTREACHED*/
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}
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#if defined (__powerpc__)
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static int buserr_detected;
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static
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void buserr(int sig)
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{
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buserr_detected = 1;
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}
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#endif
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static CARD32
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pciCfgMech1Read(PCITAG tag, int offset)
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{
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unsigned long rv = 0xffffffff;
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Read(tag=%08x,offset=%08x)\n", tag, offset);
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#endif
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#if defined(__powerpc__)
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signal(SIGBUS, buserr);
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buserr_detected = 0;
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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rv = inl(0xCFC);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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if (buserr_detected)
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{
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Read() BUS ERROR\n");
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#endif
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return(0xffffffff);
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}
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else
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#endif
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return(rv);
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}
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static void
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pciCfgMech1Write(PCITAG tag, int offset, CARD32 val)
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{
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#ifdef DEBUGPCI
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ErrorF("pciCfgMech1Write(tag=%08x,offset=%08x,val=%08x)\n",
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tag, offset,val);
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#endif
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_IGN);
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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#if defined(Lynx) && defined(__powerpc__)
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outb(0x80, 0x00); /* without this the next access fails
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* on my Powerstack system when we use
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* assembler inlines for outl */
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#endif
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outl(0xCFC, val);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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#endif
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}
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static void
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pciCfgMech1SetBits(PCITAG tag, int offset, CARD32 mask, CARD32 val)
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{
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unsigned long rv = 0xffffffff;
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#if defined(__powerpc__)
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signal(SIGBUS, buserr);
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#endif
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outl(0xCF8, PCI_EN | tag | (offset & 0xfc));
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rv = inl(0xCFC);
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rv = (rv & ~mask) | val;
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outl(0xCFC, rv);
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#if defined(__powerpc__)
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signal(SIGBUS, SIG_DFL);
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#endif
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}
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#endif /* PowerMAX_OS */
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